Digital video compression is one of the key issues in video coding, enabling efficient interchange and distribution of visual information. Significant examples of such applications are portable devices, home theatre products, etc. New applications in the field of digital television broadcasting require highly efficient robust and flexible digital video compression and encoding techniques. In this scenario, JPEG-XR, 3D/multiview video coding, and high efficiency video coding are the cutting-edge standards that have gained significant academic, research, and industrial interest. However, these standards exhibit high complexity and memory/bandwidth requirements primarily due to complex and context-aware processing, wavelet based image compression, block truncation coding techniques, adaptive/scalable algorithms, high-resolution frames, and high throughput/frame rate constraints. Moreover, several applications, including portable and wireless image/video communications, pose severe constraints on the power consumption. The power issue becomes an imperative design criterion in the era of submicron/nano fabrication technology nodes.
Advanced architecture designs are required to further reduce power consumption, compress chip area, and speed up operating frequency for high-performance integrated circuits. This special issue is dedicated to research problems and innovative solutions in all aspects of design and architecture addressing realization issues of cutting-edge standards for image and video compression. Authors are encouraged to submit high-quality research contributions. Submissions with focus on industrial value/potential are appreciated.
• Area efficient low power architectures for real time digital video compression• High speed VLSI architecture design for real time digital video compression• Novel reconfigurable and programmable architectures for emerging digital image compression• SoC/multicore architecture and hardware implementation targeting advanced video coding for image compression• Programming models, runtime systems, middleware, verification, and tool support for real time digital video compression• Real time adaptive system architectures such as reconfigurable systems in hardware and software for digital video compression• Real time architectures and design methods/tools for robust, fault-tolerant, and real-time embedded systems for Image compression• Generic and application-specific accelerators in heterogeneous architectures for real time digital image compression• High SIMD architecture for digital image compressionGuest Editorial Team• Dr. Brajesh Kumar Kaushik – Corresponding Editor Indian Institute of Technology, Roorkee Roorkee, India email: [email protected]
• Dr. Alberto Garcia Ortiz Chair for Integrated Digital Systems, ITEM University of Bremen, Germany email: [email protected]
• Dr. Berardi Sensale Rodriguez Department of Electrical and Computer Engineering University of Utah, Utah, U.S.A. email: [email protected]
Submissions should be made via the CSSP Editorial Manager platform (https://www.editorialmanager.com/cssp/default.aspx – link here).
Important dates • Manuscript submissions due November 30, 2021• First round of reviews completed & authors notiﬁed March 15, 2022• Revised manuscripts due April 30, 2022• Second round of reviews completed June 15, 2022• Final Notiﬁcation June 30, 2022• Final manuscripts due July 15, 2022• Target publication date October 2022
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