ICCAD 2020 : IEEE/ACM International Conference on Computer-Aided Design

  in Conferences   Posted on May 14, 2020

Conference Information

Submission Deadline Thursday 21 May 2020 Proceedings indexed by :
Conference Dates Nov 2, 2020 - Nov 5, 2020
Conference Address San Diego, United States
Conference & Submission Link https://iccad.com/
Conference Organizers : ( Deadline extended ? Click here to edit )

Conference Call for Papers

Paper submissions must be made through the online submission system at the ICCAD web site : https://www.softconf.com/l/iccad2020/

Deadline for Abstract Submissions: 5:00pm PDT (GMT -07:00) Thursday, May 21, 2020

Deadline for Paper Submissions: 5:00pm PDT (GMT -07:00) Thursday, May 28, 2020

Download the 2020 Call For Papers PDF.

Original technical submissions on, but not limited to, the following topics are invited:

1.1 System Design
System-level specification, modeling, and simulation
System design flows and methods
HW/SW co-design, co-simulation, co-optimization, and co-exploration
HW/SW platforms for rapid prototyping
HW/SW prototyping and emulation on FPGAs
System-level design case studies and applications
System-level issues for 3D integration
Analysis and optimization of data centers
Micro-architectural transformation
Memory architecture and system synthesis
System communication architecture
Network-on-chip design methodologies
Modeling and simulation of heterogeneous platforms
High-level synthesis for heterogeneous computing
Power/performance analysis of heterogeneous platforms
Programming environment of heterogeneous computing
Application driven heterogeneous platforms for big data, machine learning etc.
Applications and designs for systems based on optical devices
1.2 Embedded Systems and Cyberphysical Systems (CPS) and Internet-of-Things (IoT)
HW/SW co-design for embedded systems
Multi-/Many-core processor, GPU and heterogeneous SoC for embedded systems
Static and dynamic reconfigurable architectures
Domain-specific accelerators
Memory hierarchies and management
System-level consideration of custom storage architectures
Energy/power management and energy harvesting
AI and machine learning for embedded systems
CAD for IoT
Security, privacy, reliability for IoT
Edge and fog computing
Modeling and analysis of CPS systems
Dependable, safe, and secure CPS systems design
Green computing (smart grid, energy, solar panels, etc.)
CAD for application domains including wearables, health care, autonomous systems, smart cities
1.3 Neural Network and Deep Learning
Hardware and architecture for neural networks
Compilers for deep neural networks
Design method for learning on a chip
System-level design for (deep) neural computing
Neural network acceleration techniques including GPGPU, FPGA and dedicated ASICs
Safe and secure machine learning
Hardware accelerators for Artificial Intelligence
1.4 Neuromorphic Computing
Network and neuron models
Devices and hardware implementations
Non-von Neumann architectures
Event or spike-based hardware systems
CAD for bio-inspired and neuromorphic systems
1.5 Embedded Software
Real-time software and operating systems
Scheduling and execution time analysis
Middleware, virtual machines, runtime support, and resource management
Profiling and compilation techniques
Software synthesis, testing, validation, verification, and optimization
Software design for multicores, GPUs, and heterogeneous embedded architectures
Software for safe autonomy
Energy-efficient embedded software
1.6 Hardware Security
Hardware Trojans, side-channel attacks, fault attacks and countermeasures
Detection and prevention of hardware Trojans
New physical attack vectors or methods for ASICs and FPGAs
Nanoelectronic security
Hardware-based security (CAD for PUF’s, RNG, AES etc.)
Artificial Intelligence for attack prevention systems
Design and CAD for security
Security implications of CAD
1.7 Security Architecture and Systems
Embedded software forensics
Embedded software security
Trustworthy embedded software
Trusted execution environments
Cache-side channel attack and mitigation
Privacy-preserving computation
Cloud Computing data security
Internet-of-Things security
Automotive/autonomous system security
FPGA and reconfigurable fabric security
Sensor network security
Split Manufacturing for security
Supply chain security and anti-counterfeiting
1.8 Low Power and Approximate Computing in System Design
Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems
Energy- and thermal aware application mapping and scheduling
Energy- and thermal-aware architectures, algorithms, techniques
Energy- and thermal-aware dark silicon system design and optimization
Run-time management for the dark silicon
New hardware techniques for approximate/stochastic computing
2.1 High-Level, Behavioral, and Logic Synthesis and Optimization
High-level/Behavioral/Logic synthesis
Technology-independent optimization and technology mapping
Functional and logic timing ECO
Resource scheduling, allocation, and synthesis
Interaction between logic synthesis and physical design
2.2 Testing, Validation, Simulation, and Verification
High-level/Behavioral/Logic modeling and validation
High-level/Behavioral/Logic simulation
Formal, semi-formal, and assertion-based verification
Equivalence and property checking
Emulation and hardware simulation/acceleration
Post-silicon functional validation
Digital fault modeling and simulation
Delay, current-based, low-power test
ATPG, BIST, DFT, and compression
Memory test and repair
Core, board, system, and 3D IC test
Post-silicon validation and debug
Analog, mixed-signal, and RF test
2.3 Cell-Library Design, Partitioning, Floorplanning, Placement
Cell-library design and optimization
Transistor and gate sizing
High-level physical design and synthesis
Estimation and hierarchy management
2D and 3D partitioning, floorplanning, and placement
Post-placement optimization
Buffer insertion and interconnect planning
Post-synthesis optimization for FPGAs
2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization and Verification
2D and 3D clock network synthesis
2D and 3D global and detailed routing
Package-/Board-level routing and chip-package-board co-design
Post-layout/-silicon optimization
Layout and routing issues for optical interconnects

3.1 Design for Manufacturability and Design for Reliability
Process technology characterization, extraction, and modeling
CAD for design/manufacturing interfaces
CAD for reticle enhancement and lithography-related design
Variability analysis and statistical design and optimization
Yield estimation and design for yield
Physical verification and design rule checking
DFM for emerging devices (3D, nanophotonics, non-volatile logic/memory, etc.)
Machine learning for smart manufacturing and process control
Analysis and optimization for device-level reliability issues (stress, aging effects, ESD, etc.)
Analysis optimization for interconnect reliability issues (electromigration, thermal, etc.)
Reliability issues related to soft errors
Design for resilience and robustness
Reliability issues for emerging devices (3D, optical, non-volatile, etc.)
3.2 Timing, Power and Signal Integrity Analysis and Optimization
Deterministic and statistical static timing analysis and optimization
Power and leakage analysis and optimization
Circuit and interconnect-level low power design issues
Power/ground network analysis and synthesis
Signal integrity analysis and optimization
3.3 CAD for Analog/Mixed-Signal/RF and Multi-Domain Modeling
CAD for analog, mixed-signal, RF
CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electrooptical) devices, circuits, and systems
CAD for nanophotonics and optical devices
FPGA-based prototyping for analog, mixed-signal, RF systems
Analog, mixed-signal, and RF noise modeling and simulation
Device, interconnect and circuit extraction and simulation
Package modeling and analysis
EM simulation and optimization
Behavior modeling of devices and interconnect
Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)

4.1 Biological Systems and Electronics, Brain Inspired Computing, and New Computing Paradigms
CAD for biological computing systems
CAD for systems and synthetic biology
CAD for bio-electronic devices, bio-sensors, MEMS, and systems
4.2 Nanoscale and Post-CMOS Systems
New device structures and process technologies
New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.)
Nanotechnologies, nanowires, nanotubes, graphene, etc.
Quantum computing
Optical devices, computing, and communication

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