This special section attempts to create a platform to foster new ideas and technical insights in the design and analysis of emerging intelligent computing systems and their scientific, engineering, and commercial applications. In particular, we would like to focus on sustaining facile solutions using supervised machine learning, artificial neural networks, genetic algorithms, fuzzy systems, natural language processing, smart systems, and collaborative intelligence. We invite submissions of regular papers with unpublished original results and, by invitation, the revised and extended version of the papers presented in the High-Performance Computing Architectures (HPCA) Track at the 17th International Conference on Information Technology: New Generation (ITNG) (http://itng.info/).
The topics of interest are:
Artificial neural networks, Fuzzy systems, Genetic algorithms
Machine learning and data systems, Intelligent computing system architectures
Intelligent system natural language processing, Collaborative intelligence
Glow worm swarm intelligence, Intelligent interfaces and hybrid systems
Soft computing approach, Network approaches to big data science
Bio-inspired intelligent computing, Cyber intelligent computation systems
Intelligent power management schemes, Intelligence for security
Intelligent systems for environment applications, Intelligent transportation
Smart internet of things, Evolutionary computation and data science
Very large scale integrated (VLSI) circuits and systems
Neuromorphic computing and deep learning
Computational sciences, High performance computing
Artificial intelligence and emerging nano-device, Data mining on biomedical systems
Research articles must not have been published or submitted for publication elsewhere. All articles will be peer reviewed and accepted based on quality, originality, novelty, and relevance to the special issue theme. Before submission authors should carefully read over the journal\’s Author Guidelines, which is available at http://www.elsevier.com/wps/find/journaldescription.cws_home/367/authorinstructions
Papers must be submitted online at: https://www.evise.com/profile/#/COMPELECENG/login by selecting “SI-icsa” from the “Issues” pull-down menu during the submission process.
Submission of manuscript: July 31, 2019
First notification: October 31, 2019
Submission of revised manuscript: November 30, 2019
Notification of the re-review: January 30, 2020
Final notification: March 1, 2020
Final paper due: March 31, 2020
Publication date: June 2020
Fangyang Shen, PhD (Managing Guest Editor)
Computer System Technology Faculty
New York City College of Technology (CUNY)
Brooklyn, NY, USA
Mei Yang, PhD
Electrical and Computer Engineering Faculty
University of Nevada
Las Vegas, NV, USA
Maurizio Palesi, PhD
Department of Electrical, Electronics and Computer Engineering
University of Catania, Italy
F. Shen received his Ph.D. in Computer Science from Auburn University in Alabama. He is currently working as an associate professor in Department of Computer Systems Technology at New York City College of Technology (CUNY). He has over eighteen years’ research and teaching experience in wireless networks, high performance computing and STEM education. For academic services, Dr. Shen has been a technical program committee member and chair for more than fifty international conferences. He is also an associate editor, lead guest editor for multiple Journals, such as Journal of Parallel Computing and Computer and Electrical Engineering. In addition He has leaded multiple NSF Noyce projects for over three million dollars and has four years’ industrial experience in information technology.
M. Yang received her Ph. D. in Computer Science from the University of Texas at Dallas in Aug. 2003. She has been a full professor in the Department of Electrical and Computer Engineering, University of Nevada, Las Vegas since 2016. Her research interests include machine learning, computer architectures, networking, and embedded systems. She has published over 150 peer-reviewed conference and journal papers in these areas. She has served on the editorial board of several international journals and organization committee of numerous international conferences.
M. Palesi is Associate Professor in Computer Engineering at the Department of Electrical, Electronics and Computer Engineering, Università degli Studi di Catania, Catania, Italy. His research activity is focused in the area of embedded systems with particular emphasis on single-chip implementations based on the network-on-chip design paradigm. He is co-author of 50 papers in international journals, 6 book chapters, 70 papers in international conferences/symposium/workshops, and co-author of a book. He has been recipient of the best paper award at the Design Automation and Test in Europe and the HiPEAC paper award 2014. Dr. Palesi has served as Guest Editor of 17 special issues in top-level journals, including, IET Computers & Digital Techniques, ACM Transactions on Embedded Computing Systems, International Journal of High Performance Systems Architecture. He has served as General Chair and TPC Co-Chair in several international conferences and workshops. He serves as Associate Editor in 12 international journals. He is member of the European Network on High Performance and Embedded Architecture and Compilation (HiPEAC) and IEEE Senior Member.