Sergi Abadal, Universitat Politècnica de Catalunya, Spain
Salvatore Monteleone, University of Catania, Italy
Kun-Chih Chen, National Sun Yat-sen University, Taiwan
Maurizio Palesi, University of Catania, Italy
Aims and Scope
Recent years have witnessed the emergence of computing architectures that integrate up to a thousand processor cores and memory on a single die as a result of relentless semiconductor device scaling. This opens up a plethora of architectural challenges in terms of efficiency or specialization, among others, and supports the spread of various applications and novel computational paradigms, ranging from massive manycore processing to reconfigurable, quantum, in-memory, or neuromorphic computing.
As a side effect of such wild increase in integration, communication (and not computation) has gradually become the main determinant of performance in nowadays computers. To address this, processors integrate interconnection networks that manage the movement of data in a scalable and cost-effective manner at the chip scale, i.e., for ranges between hundreds of nanometers to a few millimeters. The main challenge is for these chip-scale nanonetworks to provide the efficiency, versatility, scalability and reliability necessary to tackle the growing technological, architectural and workload heterogeneity in this new era of computing.
The special issue seeks contributions addressing the different challenges of chip-scale nanocommunications and networking, putting emphasis on emerging technologies (e.g., wireless, RF interconnects, optics), new approaches (e.g., approximate computing, machine-learning-based design) and disruptive applications (e.g., quantum computers). The editors equally welcome submissions about physical prototypes realizable in the near future and more prospective contributions with clear longer-term potential. While the scope of the special issue revolves around communications and networking aspects, submissions discussing frontier aspects such as memory architectures, 2.5D/3D packages, or application mapping are also welcome.
Topics of Interest
The special issue solicits high-quality and original contributions on topics including, but not limited to:
Wireless chip-scale nanonetworks: mmWave-THz channel models, on-chip antenna design, transceiver implementation, MAC protocols, graphene-based wireless designs, wireless manycore architectures, hybrid wired-wireless nanonetworks.
Nanophotonic chip-scale nanonetworks: integrated nanophotonic component design, laser integration, novel network architectures, thermal-aware design, optical-wireless channel modeling.
Integrated 2.5D/3D nanonetworks: stacked and monolithic 3D Network-on-Chip (NoC), TSV placement, TSV-aware topologies, thermal-aware routing, multicast and broadcast in 3D NoCs, off-chip communication in interposer-based systems
Machine learning (ML) and NoC-based systems: Interconnects for ML systems/accelerators, Memory access for the NoC-based ML systems, NoC-based ML algorithm design.
Communication within quantum computers: qubit mapping, SWAP-aware routing algorithms, qubit shuttling and swapping mechanisms, multi-chip quantum architectures.
Approximate computing for NoC and NoC-based systems: approximate communication in on-chip networks, approximate computing-communications interplay, adaptive error control.
NoC in emerging architectures/applications: NoCs for FPGAs, ASICs, heterogeneous systems; neural network accelerators, massive manycore processors, neuromorphic (spike-based) computers, software-defined metamaterials, programmable matter.
Extreme embedded nano-systems: real-time, mission-critical, intermittent computing, energy-harvesting-based embedded networks.
Quantum Cellular Automata: integrated communication modules, prototypes, QCA-network-on-chip.
NoC architecture and implementation: impact of novel technologies to topologies, routing, flow control, QoS management, reliability, security, design methodologies and tools, application mapping. Real and industrial NoC case studies.
Prospective authors shall submit their papers through the submission portal, choosing the option “VSI: Chip-Scale Nanonetworks” in the issue selection stage. The submitted manuscripts should not have been previously published nor should be currently under consideration for publication elsewhere.
This special issue follows a continuous and expedited review process. Papers will be start being reviewed shortly after they are submitted. The review-to-acceptance process is aimed at being no longer than 4 months.
Manuscript submissions due: 20 March 2020
Notification of acceptance: 1 July 2020
Final manuscripts due: 15 July 2020
Request for Information
Sergi Abadal (email@example.com)