ISVLSI 2021 : IEEE Computer Society Annual Symposium on VLSI

  in Conferences   Posted on October 30, 2020

Conference Information

Submission Deadline Sunday 21 Feb 2021 Proceedings indexed by :
Conference Dates Jul 7, 2021 - Jul 9, 2021
Conference Address Tampa, United States
Conference & Submission Link http://www.eng.ucy.ac.cy/theocharides/isvlsi21/
Conference Organizers : ( Deadline extended ? Click here to edit )

Conference Ranking & Metrics (This is a TOP Conference)

Impact Score 2.97
#Contributing Top Scientists 35
#Papers published by Top Scientists 58
Google Scholar H5-index 9
Guide2Research Overall Ranking: 257
Category Rankings
Hardware, Robotics & Electronics 43
Proceedings https://ieeexplore.ieee.org/xpl/conhome/1000807/all-proceedings

Conference Call for Papers

The 2021 Symposium explores emerging trends and novel ideas and concepts covering a broad range of topics in the area of VLSI: from VLSI circuits, systems and design methods, to system level design issues, to bringing VLSI design to new areas and technologies such as nano- and molecular devices, security, artificial intelligence, and Internet-of-Things, etc. Future design methodologies and new EDA tools are also a key topic at the Symposium. Over three decades the Symposium has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI, bringing together leading scientists and researchers from academia and industry. The ISVLSI proceedings will be indexed in the IEEE Xplore Digital Library. Selected high quality papers will be further invited for submission to a journal special issue. The Symposium has established a reputation in bringing together well-known international scientists as invited speakers. The emphasis on high quality will continue at this and future editions of the Symposium.

Contributions are sought in the following areas:

1) Circuits, Reliability, and Fault-Tolerance (CRT): analog/mixed-signal circuits design and testing, RF and communication circuits, adaptive circuits and interconnects, design for testability, online testing techniques, static and dynamic defect- and fault- recoverability, variation aware design, VLSI aspects of sensor and sensor network.

2) Computer-Aided Design and Verification (CAD): hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis, statistical approaches.

3) Digital Circuits and FPGA based Designs (DCF): digital circuits, chaos/neural/fuzzy-logic circuits, high speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.

4) Emerging and Post-CMOS Technologies (EPT): nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.

5) System Design and Security (SDS): structured and custom design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, hardware security, cryptography, watermarking, and IP protection, TRNG and security-oriented circuits, PUF circuits.

6) VLSI for Applied and Future Computing (AFC): Neuromorphic and brain-inspired computing, quantum computing, circuits and architectures for machine learning and artificial intelligence, methodologies for on-chip learning, deep learning acceleration techniques, applications for and use-cases of learning systems, sensor and sensor network, electronics for Internet of Things and smart medical devices.

The symposium program will include technical sessions by contributed papers and invited speakers by the Program Committee as well as a poster session. The keynotes, panels, special sessions, research demo sessions, and Student Research Forum are planned as well. Authors are invited to submit full-length, original, unpublished manuscripts in IEEE proceedings format (up to 6 pages). To enable blind review, the author information should be omitted from the submission.

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